A 3.3 V 16 Mbit DRAM-compatible flash memory
R. Fackenthal, P. Kwong, Duane Mills, Sanjiv Sambandan, S. Sweha · 2002
A new 16 Mb (1 Mbit/spl times/16) flash memory on a 0.6 /spl mu/m CMOS process has been designed, that combines the high-speed code execution capabilities of DRAM with nonvolatile, high-density, updatable code storage of flash memory, thus replacing the traditional redundant memory paradigm with one cost-effective solution. This solution eliminates the need to shadow code from nonvolatile memory to DRAM, thus enabling design of direct-execute code and mass storage memory systems, while the fully DRAM-compatible interface allows glueless design with existing DRAM controllers.