Hierarchical test assembly for macro based VLSI design
Jens Leenstra, Lambert Spaanenburg · 2002
A novel incremental procedure for the hierarchical assembly of macro test specifications into a chip test program is presented. To solve test generation/application problems, a bottom-up symbolic test assembly procedure that proceeds in line with the construction of the system is proposed. It is shown that for a modular design approach, this procedure can be extended with design-for-testability features to ensure that all macro tests are assembled into a chip test program. The approach is exemplified by the design of a decimation filter for a Sigma / Delta A/D (analog-to-digital) converter.>