A programmable BIST architecture for clusters of multiple-port SRAMs
Alfredo Benso, Stefano Di Carlo, Giorgio Di Natale, P. Prinetto, M. Lobetti Bodoni · 2002
This paper presents a BIST architecture, based on a single microprogrammable BIST processor and a set of memory wrappers, designed to simplify the test of a system containing many distributed multi-port SRAMs of different sizes (number of bits, number of words), access protocol (asynchronous, synchronous), and timing.