Unrolled Polar Decoders, Part I: Hardware Architectures.
Pascal Giard, Gabi Sarkis, Claude Thibeault, Warren J. Gross · arXiv (Cornell University) · 2015
This is the first in a two-part series of papers on unrolled polar decoders. In this paper (Part I), we present a family of architectures for hardware polar decoders using a reduced-complexity successive-cancellation decoding algorithm. The resulting fully-unrolled architectures are capable of achieving a coded throughput in excess of 400 Gbps on an FPGA, two orders of magnitude greater than current state-of-the-art polar decoders. Moreover, the proposed architectures are flexible in a way that makes it possible to explore the trade-off between resource usage and throughput.