A hardware accelerator board for cellular neural networks: CNN-HAC
T. Roska, G. Bártfai, P. Szolgay, Tamás Szirányi, András G. Radványi, Tibor Kozek, Z. S. Ugray · IEEE International Workshop on Cellular Neural Networks and their Applications · 2002
The hardware accelerator (HAC) boards using catalog programmable VLSI ICs represent a trade-off having higher reconfigurability and lower cost. This paper presents such a solution for a cellular neural network (CNN). The architecture of the present design (CNN-HAC) using 4 standard DSPs to calculate the transient response of a one-layer CNN containing 0.25-1.0 million analog neural cells is presented. The architecture and also the design principles are independent of the number of processors. The actual design was made in the form of a PC add-on board. The global control unit, which connects the board to the host firmware and communicates control signals to/from the local control units of the DSPs, was realized mainly with EPLDs. A special correspondence between the virtual processing elements-calculating the time discrete models of the analog neural cells-and the physical ones, established to work an architecture with an infrequent, one-directional interprocessor communication, is discussed in detail.>