A VLSI fuzzy processor with parallel rule execution
Marcel Jacomet, Roger Wälti · Proceedings of IEEE 5th International Fuzzy Systems · 2002
This paper describes the architecture of a VLSI fuzzy processor, which is fabricated in the 0.7 /spl mu/m digital CMOS technology from ES2. Due to the parallel architecture of the fuzzy rule block, very high performance is achieved. The architecture supports fine tuning and optimization of fuzzy systems by the possibility to weight each fuzzy rule separately.