Parallel evolutionary graph generation on a PC cluster and its application to multiple-valued circuit synthesis
Masanori Natsui, Takafumi Aoki, T. Higuchi · 2003
This paper presents an efficient graph-based evolutionary optimization technique called evolutionary graph generation (EGG) and its extension to a parallel version. The parallel EGG system presented in this paper is based on a coarse-grained model of parallel processing and is implemented on a 16-node Linux PC cluster. The potential capability of parallel EGG system is demonstrated through the synthesis of a radix-4 signed-digit (SD) full adder circuit.