CMOS VLSI implementation of the 2D-DCT with linear processor arrays
U. Totzek, F. Matthiesen, S. Wohlleben, Thomas Noll · International Conference on Acoustics, Speech, and Signal Processing · 2002
The design of a test chip for the computation of the two-dimensional discrete cosine transform (2D-DCT) is described. Different chip architectures based on a matrix formulation of the 2D-DCT algorithm are developed systematically. Circuit and layout for one architecture, selected for a 1.5- mu m CMOS test chip, are presented. The test chip computes the DCT and its inverse with high accuracy, meeting the CCITT specification standard, for a block size of 8*8 with a 45-MHz and for a block size of 16*16 with a 22.5-MHz pixel rate under worst-case conditions.>