Area reduction techniques for BIST PLA's
Enrico Macii, Tilman Wolf · 2002
Programmable Logic Arrays (PLA's) are widely used in VLSI systems because of their compactness, ease in automatic design, and regularity in their structure. This paper describer some techniques to reduce the chip area of a PLA containing self-testing circuitry. In particular, we introduce some variants to the method presented which allow us to further minimize the amount of logic required to realize the BIST mechanism. Some experimental results on the implementation of a real self-testing PLA are given in order to show the effectiveness of our approach.>