DFT & ATPG: together again
B. Mathew, Daniel G. Saab · 2002
A system which adds DFT and generates test vectors for the enhanced circuit is described. Partial reset, observability enhancement and partial scan are employed. A dynamic partial reset flip-flop selection method is described utilizing a fast genetic algorithm based sequential test generator. This system trades off various parameters to obtain high fault coverage, low test application times, low hardware overhead and low CPU time.