On the IC architecture and design of a 2 µm CMOS 8 MIPS digital signal processor with parallel processing capability: The PCB5010/5011
F. van Wijk, F.P.J.M. Welten, Jef van Meerbergen, Jan Stoter, Jos Huisken, A. Delaruelle, K. van Eerdewijk, J. Schmid, Joern Wittek · 2005
A 2µm CMOS Digital Signal Processor (PCB5010 / PCB5011), capable of eight million instructions per second (8MIPS), and up to 6 concurrent operations in each instruction will be described [1]. This high throughput results from a highly parallel architecture (see Fig. 1) with high-speed data handling capability. It contains two 16b data buses, two primary execution units, five I/O interfaces, a data ROM, two data RAMs, and flexible addressing of on and off-chip memory using three address computation units. Benchmarks show a two to six times improvement in overall performance over its predecessors.