Buffer implementation for Proteo network-on-chip
Ilkka Saastamoinen, Mikko Alho, Jari Nurmi · 2003
Proteo is a synthesizable packet switched NoC (Network-on-Chip) architecture which is built from a library of interconnect IP (Intellectual Property) blocks,. The library includes two types of blocks: interfaces to the network and routing nodes, which are the building blocks of the actual communication structure. When it is necessary to store packets, they are placed in FIFO buffers in the interconnect IPs. Compared to the control logic the buffers are functionally simple, but in networks they consume most of the silicon area. However the smaller the buffers are, the greater is the possibility that some traffic is lost. In this paper the properties of buffers are studied with a test network. Gate-level estimates of area of the networks, were generated using 0.18 /spl mu/m technology. Performance of the networks and utilization of buffers in the networks were studied by simulation. Simulation and synthesis show that there exists an optimal point where the product of the required silicon area and the required clock cycles of the simulation is minimized. Since buffers consume most of the silicon area in the networks, the results show that it is necessary to adjust packet and buffer sizes, when an optimal cost/performance ratio of the network is desired.