Design issues of deep submicron wave pipelining technology
Lan Chen, Tang Zhimin · 2002
This paper introduces strategies for developing wave pipelined systems with deep submicron manufacture technology. The delay model for interconnect wire under deep submicron technology is discussed in detail. With data transport path balancing and routing strategies introduced in this paper, the clock-rate of a wave pipelined circuit can achieve a speedup of 3 to 6.