Memory allocation method for indirect addressing with an index register
Y. Kaneko, Nobuhiko Sugino, Akinori Nishihara · Asia Pacific Conference on Circuits and Systems · 2003
Digital signal processors (DSPs) commonly employ indirect addressing mode using an address register (AR). For such DSPs, reduction in overhead codes over memory access is quite important in order to generate efficient codes. In some DSPs, an index register (IX) is provided in the addressing mode. For further reduction in overhead codes, the memory allocation method utilizing such an IX update operation is considered in this paper. In order to reduce the overhead codes, two algorithms are applied. The purpose of the first algorithm (4.1 Lower variance in the AR modification) is to obtain an allocation, which is convenient for IX. The purpose of the second algorithm (4.2 Memory a location method with less AR loads) is to make the best use of AR and IX.