An advanced pulse compression processor
J.W. Ianniello, F. Stroili · IEEE Conference on Aerospace and Electronics · 2002
A digital pulse compression processor for an airborne radar system is described. The processor implements a general-purpose convolution-based algorithm that enables pulse compression of any waveform subject to the radar real-time throughput requirements. The pulse compression processor uses very high speed integrated circuit (VHSIC) level technology and uses multichip packaging to achieve a small size compatible with airborne applications. It is developed in a modular structure to enable custom application of common modules to platforms with different requirements. The processor architecture, an analysis of throughput capability, the modular building blocks, and the integrated circuit and packaging technology are presented. Two specific designs are described, and the performance and physical characteristics of the designs for both the VLSI and modular VHSIC versions are compared. Future improvements that will enable a halving of the size and a doubling of the operation rate are presented.>