Low-Leakage Repeaters for NoC Interconnects
Arkadiy Morgenshtein, Israel Cidon, Avinoam Kolodny, Ran Ginosar · 2005
Several low-leakage repeater circuits for network-on-chip (NoC) interconnects are presented and analyzed for various utilization rates. The recently proposed staggered-Vt (SVT) repeater is compared with the novel dual-Vt domino (DTD) repeaters and sleep repeaters (SR). These circuits are compared with standard low-Vt (LVT) repeaters in a 32-bit link. Up to 70% and 61% power reduction was obtained in SVT and DTD repeaters, respectively. DTD repeaters are the most area-efficient ones, showing 40% reduction in total area of repeaters. Sleep repeaters are most area-consuming and less effective in high and moderate utilization rates, but comparable to SVT in terms of power for utilization rates below 2%, showing 72% power reduction.