A novel VLSI architecture for clustering analysis
Mao‐Fu Lai, Chaur‐Heh Hsieh · 2002
This paper presents a novel VLSI architecture for the squared-error clustering algorithm. The proposed architecture reduces the huge number of processing elements (PEs) required by the other previous architectures. The system uses only local communication between adjacent PEs, and it is modular, regular, and expandable. The VLSI implementation of high speed clustering analysis can be realized with significantly less circuit complexity based on the proposed architecture.