A programmable VLSI neural network processor for digital communications
Joongho Choi, Sa Hyun Bang, B.J. Sheu · 2002
An analog VLSI neural network processor is developed for digital communication receiver applications without any need for a priori estimation of the channel characteristics. Network training is performed by the modified Kalman filtering algorithm to speed up the convergence process for intersymbol interference and white Gaussian noise communication channels. The fabricated chip is based on a four-layered network running at 1 MHz in a 2-/spl mu/m CMOS technology. Measured characteristics of the electrically programmable wide-range synapse cell, the input neuron, and the output neuron are supportive of precision network operation.