VLSI implementation of a modular ANN chip for character recognition
Sameh Ebrahim Rehan, M.I. Elmasry · 2002
Dedicated mixed-mode VLSI chips, which provide a compact, fast, and flexible implementation of ANNs, can release the full power of these structures. In this paper, a sampled-data implementation of ANNs is presented. ANN model and circuit simulations are performed for a prototype MLP model architecture which solves two-character recognition problems. A novel modular ANN chip, which implements a two-character recognizer using a parallelogram VLSI architecture, is designed using a 1.2 /spl mu/m CMOS technology. An extended architecture is proposed to solve multi-character recognition problems. This paper demonstrates the feasibility of a CMOS VLSI implementation of ANNs for character recognition using the developed modular ANN chip.>