A 10 ns, 4000 gate, 160 pin CMOS EPLD developed on a 0.8 μm process
Rakesh H. Patel, Myron Wong, D. Reese, J. Costello, J. Turner · 2002
The 160-pin EPM7192, an erasable programmable logic device (EPLD) with a system operating frequency in excess of 100 MHz, is described. This 192 macrocell device is the fastest EPLD at this logic density. The input to output propagation delay for this device was measured to be 9.8 ns. The clock to output propagation delay was clocked at 4 ns. This device uses a combination of architectural, process, and circuit improvements to achieve high performance and logic densities. The EPM7192 is implemented on a 0.8-/spl mu/m CMOS-EEPROM (electrically erasable programmable read-only memory) technology.