A hybrid approach to design error detection and correction [VLSI digital circuits]
Andreas G. Veneris, Ibrahim N. Hajj · 2003
With the increase in the complexity of VLSI circuit design, logic design errors can occur during synthesis. In this work, we present a method for multiple design error diagnosis and correction. Our approach uses the results of test vector simulation for diagnosis and employs BDDs during correction so that it remains both computational efficient and accurate. Experimental results on ISCAS'85 benchmark circuits show that our approach can typically detect and correct 2 and 3 errors within seconds of CPU time.