A multi-processor cellular automaton chip
Ken Steiglitz, Ryuta Morita · 2005
We describe the design and testing of an 18- processor chip that implements the update rule for a fixed one-dimensional binary-valued cellular automaton. The VLSI design was done in the high level, procedural language ALLENDE [5,6]. The processors are bit-serial, completely pipelined, and cascaded, so that one chip performs 18 updates per major clock cycle. In principle, any number of chips can be cascaded, with a corresponding linear speedup. Sixteen chips were fabricated in 4 µ nMOS using the MOSIS facility, of which 10 were fully functional. When tested, 9 of the fully functional chips operated at maximum clock rates between 6 and 8 Mhz. This implies a maximum speed of about 108bit updates per second per chip, and opens the way for experimentation that is too time-consuming using general purpose devices.