Loop list scheduler for DSP algorithms under resource constraints
C.-Y. Wang, Keshab K. Parhi · 1993 IEEE International Symposium on Circuits and Systems · 2002
A new algorithm for resource-constrained scheduling for DSP applications is presented. New graph dependent constraints are defined. This directly results in the smallest iteration period for any data-flow graph. Previous synthesis systems have focused on simple DSP algorithms which contain no recursive loops or have single delays in the recursive loops. The MARS system is not restricted to such algorithms. This approach exploits inter-iteration precedence constraints, and incorporates implicit retiming and pipelining in generating optimal and near optimal schedules.>