Methodologies for automated synthesis of memory and interconnect subsystems in parallel architectures
Gallo, Luca · Università degli Studi di Napoli Federico II · 2015
As frequency scaling for single-core computers has today reached practical limits, the only effective source for improving computing performance is parallelism. Consequently, automated design approaches leveraging on parallel programming paradigms, such as OpenMP, appear a viable strategy for designing on-chip systems. At the same time, emerging architectures, such as reconfigurable hardware platforms, can provide unparalleled performance and scalability; in fact they allow to customize memory and communication subsystems based on the application needs. However, current high level synthesis tools often lack enough intelligence to capture those opportunities consequently leaving room for research. As a first contribution of this thesis, a novel technique based on integer lattices is proposed for tailoring the memory architecture to the application accesses pattern. Data are automatically partitioned across the available memory banks reducing conflicts so as to improve performance. Compared to existing techniques, the rigorous spatial regularity of lattices yields more compact circuits. As a second aspect, in order to sustain the execution parallelism stemming from the presence of multiple memory banks, an efficient interconnection subsystem must be designed. To this aim, the thesis proposes a methodology capable of targeting the interconnect to the traffic profile imposed by the distributed memory. In conclusion, all the proposed techniques are merged together in a comprehensive OpenMP-based design flow, resulting in an automated framework that well fits in the electronic design automation panorama.