A low power survivor memory unit for sequential Viterbi-Decoders
M. Traber · 2002
This paper introduces an innovative, low-power algorithm for survivor memory units (SMU) in Sequential Viterbi-Decoders (VD), called "Path-Metric Controlled Decision Save" (PCDS). Based on the fact that theoretically only the decisions of the survivor states are necessary for decoding, one can neglect all the other decisions from non-survivor states, i.e. we do not have to save them in the survivor memory and hence reduce power consumption significantly. The only problem is to derive a criterion which distinguishes between the essential and negligible decisions. It will be investigated and proven that the performance loss introduced by the PCDS algorithm is confidently negligible for all SNR and that the PCDS algorithm is self-adaptive in terms of performance. Furthermore, it will be illustrated that, for state of the art VD. e.g. HDSL2 or SDSL, the power reduction exceeds 90% whereas the area-overhead for this algorithm is a comparator and hence negligible.