A two-chip CMOS 64 b mainframe processor chipset
M. Yamagishi, K. Koide, A. Ishiyama, A. Yamagiwa, T. Hayashi, Y. Satou · 2002
A two-chip processor chipset with a full set of mainframe instructions is presented. One chip decodes instructions and executes arithmetic and logic operations. The other chip controls a buffer storage (cache) and translates logical addresses into physical. A hybrid of four-stage and five-stage pipelines and an on-chip microcode storage are adopted to execute LD/ST (load/store) and most R-R (register-register) instructions in a single cycle. Six kinds of macro cells and a macro-oriented clock distribution system are used to obtain a machine cycle time of 18 ns (typical). The chips are fabricated using 0.8- mu m CMOS triple-metal layer technology and are each housed in a 400-pin PGA package.>