High performance array processor for video decoding
Jooheung Lee, N. Vijaykrishnan, M.J. Irwin · 2005
In this paper, high performance array processor for signal processing algorithms with high computational complexities is implemented using 0.16 /spl mu/m CMOS standard cell library. The proposed array processor consists of simple processing elements. The architectural benefits of highly regular, parallel, and pipelined processing elements simplify the design of complex signal processing systems and enable high throughput rate by massive parallel computations. We show the utility of the proposed architecture as a configurable core by mapping inverse discrete cosine transform (IDCT), motion compensation (MC), and inverse quantization (IQ) onto the proposed fabric. In addition, we propose a novel scheme that integrates the inverse quantization part of video decoding into the 2-D IDCT process simplifying computational logics. The results show that a high throughput rate to meet the real-time requirement is effectively achieved by exploiting the properties of both compressed video data statistics and the array processor architecture.