Testing of a parallel ternary multiplier using I/sup 2/L logic
Mallika De, Bhabani P. Sinha · 2002
A generalized model for faults in multivalued I/sup 2/L circuits has been proposed. Using this model, the test sets have been generated for testing the basic modules of a parallel multiplier using multivalued I/sup 2/L technology. These basic modules include four input balanced ternary full adder and a precarry generator, each of which has multivalued current inputs and outputs. The generated test sets can detect single faults (either 'stuck-at' or 'skew' type) in these circuits.