Synthesized self-timed synchronous systems
Richard Auletta · 2003
Communicating sequential processes (CSP) is used as the specification language for the synthesis of self-timed synchronous circuits. VHSIC hardware description language (VHDL) is used as the intermediate representation for synthesis with existing logic and high level synthesis tools. This approach preserves the functional properties of the CSP specification while allowing temporal properties to be enforced within the digital domain.>