Behavioural VHDL code generation for synchronous FSMs
X.J. Wang, S. Grainger, A. Cooper · 2003
An interactive system, HLSS, that generates behavioral VHDL (VHSIC Hardware Description Language) code for synchronous finite state machines (FSMs) is described. A process model graph that separates the combinational and sequential logic elements in a FSM is used in code generation. The generated code can be used for synthesis as well as simulation. A complete example is given.>