Gate-level fault diagnosis for scan-based VLSI environment
YunSheng Xu, Xiaowen Sun · 2002
This paper presents a gate-level fault diagnostic scheme for integrated circuits with STUMPS based built-in self-test (Bardell and McAnney 1982). It first employs a structural analysis algorithm to eliminate modeled faults that do not produce observed erroneous circuit outputs, then uses a dynamic fault dictionary and signature simulation technique to improve on the fault diagnostic resolution.