A C-testable modified Booth's array multiplier
Syed Mahfuzul Aziz · 2002
In this paper, a C-testable parallel multiplier based on modified Booth's algorithm is presented. The gate-level design requires only 20 vectors to detect all single stuck-at faults. It does not require any extra logic and has no delay overhead compared with the basic non-C-testable design. Five extra inputs are required for the C-testable multiplier, this number can be reached to four using a small amount of extra logic. The multiplier has a regular structure and therefore suitable for use in a silicon compiler.