Static test compaction for IDDQ testing of sequential circuits
Yoshinobu Higami, Kewal K. Saluja, K. Kinoshita · 2002
This paper presents a static test compaction method for IDDQ testing of sequential circuits. Target faults are bridging faults between arbitrary pair of nodes including internal nodes, signal lines, VDD and GND. In the proposed method, test subsequences are removed and replaced with shorter subsequences.