Testing issues on high speed synchronous DRAMs
Wha-Joon Lee · 2002
The test programming becomes very much complicated due to functionality and special features implemented in SDRAMs. Considering the combination of speed variations and operational modes, the number of the test items would easily exceed beyond the acceptable limit. The SDRAM testing issues are listed as follows: high speed tests with a slow production tester; load board and load circuit design for high speed testing; and test program development for the new features.