A new motion estimation core dedicated to H.263 video coding
Gen Fujita, Takao Onoye, Isao Shirakawa · 2002
A VLSI architecture of a motion estimator is described for the H.263 low bitrate video coding. Adopting an efficient hierarchical search algorithm, a new motion estimator yields high quality vectors with small area occupancy and at a low operation frequency. A one-dimensional Processing Element array is devised to be tuned to the H.263 encoding, which treats both the advanced prediction mode and the PB-frame mode. The proposed motion estimation core is integrated in 1.34 mm/sup 2/ by using 0.35 /spl mu/m CMOS 3LM technology, which operates at 15 MHz, and hence enables the realtime motion estimation of QCIF pictures.