Diagnosing combinational logic designs using the single location at-a-time (SLAT) paradigm
Thomas Bartenstein, D. Heaberlin, Leendert M. Huisman, D. Sliwinski · 2002
A new way of diagnosing ICs that fail logic tests is described. It can handle bridging fault, opens, transition faults and many more complex defects as easily and as accurately as regular stuck-at faults.