JPEG encoder system-on-a-chip demonstrator
J.K. Hunter, John V McCanny, A. Simpson, Yi Hu, James G. Doherty · 2003
The design of a system-on-a-chip (SoC) demonstrator for a baseline JPEG encoder core is presented. This combines a highly optimised discrete cosine transform (DCT) and quantization unit with an entropy coder which has been realised using off-the-shelf synthesisable IP cores (run-length coder, Huffman coder and data packer). When synthesised in a 0.35 /spl mu/m CMOS process, the core can operate at speeds up to 100 MHz and contains 50 k gates plus 11.5 kbits of RAM. This is approximately 20% less than similar JPEG encoder designs reported in literature. When targeted at FPGA the core can operate up to 30 MHz and is capable of compressing 9-bit full-frame color input data at NTSC or PAL rates.