Biased two's complement representation for low-power DSP systems
Kei-Yong Khoo, Chao-Liang Chen, Alan N. Willson · 2002
This paper shows that the switching activity of the sign-extended bits in a two's complement number in a DSP system can be reduced by the application of a bias to the system's input. The technique is easy to implement and requires only one to two additional adders. Experimental results show a 20% and 5% reduction in bit-switching activities for a typical voice grade signal and an FIR filter processing the signal, respectively.