VLSI-efficient implementation of full adder-based median filter
A. Burian, Jarmo Takala · 2004
A new VLSI-suitable hardware implementation of the median filter that uses full adders (FAs) as the basic building block is introduced. The proposed hardware structures consist of several stages that exhibit regular and modular structure. It also reduces the hardware requirements and has a faster processing speed, when compared with some other existing hardware implementations. A general methodology for designing full adder-based median filters is also developed.