An efficient VLSI architecture for 2D-DCT using direct method
Bian Li Jian, Zeng Xuan, Tong Jia Rong, Liu Yue · 2002
An efficient VLSI architecture for 8/spl times/8 two-dimensional (2D) discrete cosine transform (DCT) is proposed in this paper. It is a folded architecture using direct method. It can compute 2D-DCT of a 12-b 8/spl times/8 block using one 1D-DCT unit without transpose memory. Taking advantage of the direct method, the total number of multiplications in the proposed architecture is only half of that required for row-column method. It, in turn, results in the doubled operating speed compared with those conventional implementations with row-column method. Under 0.6 /spl mu/m CMOS and double metal technology, the proposed architecture presents a chip with core size 3.9/spl times/0.9 mm/sup 2/, transistor count 114 K and clock rate 200 MHz.