Design methodology of a test chip for a portable 8ns 10 ports register file
L. Lucas, Alain Greiner · 2002
This paper presents the design methodology used to implement a test chip for a multiport register file, as well as, the motivation of the project. The register file contains 6 read buses, 4 write buses, and 64 words of 32 bits. A built-in-self test scheme has been used to validate the register file. The final test chip contains 65000 transistors. The complete design including high level models took one man-month.