The Effects of Architecture on the Performance on Latency Hiding Via Rapid Context Switching.
Rajat Mukherjee, John K. Bennett, J. Greenwood · 1995
We study the effects of cache organization, caching policy and network capacity on the performance of latency hiding via fast context switching in largescale shared memory multiprocessors. We describe a technique that supports hardware or softwareinitiated switches that works on a commercially available processor with register windows. Significant performance improvements (120%) can be achieved with latency hiding when cache miss latency is high, even with low cache miss rates (1 - 2%) and relatively large thread switch overhead (30 cycles). Write-back, setassociative caches provide best latency hiding performance, especially with constructive cache interference. We also show that increased processor utilization can significantly increase contention on the underlying network. Key Phrases: Shared Memory Multiprocessors, Latency Hiding, Context Switching, Architecture. 1 Introduction Memory system performance is critical in largescale shared memory multiprocessors since limited interc...