Integration of SRAM redundancy into production test
J. Jayabalan, J. Povazanec · 2003
In this paper, we present the implementation of a multiple-SRAM redundancy concept, which increases the yield of a 100 mm/sup 2/, 0.18 micron technology device with a total memory size of 3 Mbits, by a factor of 20%. A number of test and design considerations are detailed.