A semi-direct method for design verification of array chips
David A. Zein, O.P. Engel, Gary S. Ditlow · 2002
An experimental general-purpose program based on ICD has been created to aid in the design of bipolar array chips. The program consists of a unique automated set of tools that verify the logic function of every chip circuit, determine signal noise margin, and provide reliability guideline checking for contact studs. The program was originally developed as part of analog and logic design verification tools to audit the design of a 48 Kb bipolar array cache chip prior to release to manufacturing. The analytic tools used consist of a semidirect method of analysis, a Gray algorithm, recognition of differential pairs to minimize the number of simulations (DC reruns), and a set of techniques to take into account the peculiarities of bipolar circuits, such as emitter and collector dots, input-output loading conditions, differential pairs, and the presence of a mixture of digital, sequential, and analog circuits. As a result, the design verification of 60 distinct circuits (books) of the 48 K chip took less than three CPU minutes on an IBM 3090 computer.>