High-level design synthesis with redundancy removal for high speed testable adders
M. Wagh, C.-I.H. Chen · 2003
Current synthesis tools are capable of handling area and timing constraints. Synthesis for testability process ensures that the design is testable. In this paper CAD tools capable of handling the testability requirements are explained and emphasis is on redundancy removal for designing high speed testable binary adders. The 1.2 /spl mu/m CMOS realization of the 32-bit testable adder performs the addition operation in 4.09 ns. Removal of redundant logic yields a 100% testable design with significant improvement in performance characteristics. A 15% improvement in speed and a 25% reduction in overall area has been observed when compared with the untestable design.