A fast sort-selection filter chip with effectively linear hardware complexity
James A. Roskind · 2005
A hardware architecture for obtaining the t(th) largest number from a list of N numbers, each B bits long is presented. When t is such that N=2t-1, the system described is a hardware median filter. It is also shown that a pipelined architecture can perform a real-time filtering operation at a rate of one median computation per cycle, where the cycle time of this system is proportional to\log N. This hardware selection architecture is currently being implemented on a VLSI chip (7K gates plus testability structures) to build an N=25 median filter with a throughput rate for image processing of better than 10M pixels/second with 8 bits/pixel. This architecture can also be used as an efficient basis of a hardware sorter.