Exploring scaling limits and computational paradigms for next generation embedded systems
Andrey Vladimirovich Zykov · ProQuest Demo Repository · 2009
It is widely recognized that device and interconnect fabrics at the nanoscale will be characterized by a higher density of permanent defects and increased susceptibility to transient faults.This appears to be intrinsic to nanoscale regimes and fundamentally limits the eventual benefits of the increased device density, i.e., the overheads associated with achieving fault-tolerance may counter the benefits of increased device density -density-reliability tradeoff.At the same time, as devices scale down one can expect a higher proportion of area to be associated with interconnection, i.e., area is wire dominated.In this work we theoretically explore density-reliability tradeoffs in wire dominated integrated systems.We derive an area scaling model based on simple assumptions capturing the salient features of hierarchical design for high performance systems, along with first order assumptions on reliability, wire area, and wire length across hierarchical levels.We then evaluate overheads associated with using basic fault-tolerance techniques at different levels of the design hierarchy.This, albeit simplified model, allows us to tackle several interesting theoretical questions: (1) When does it make sense to use smaller less reliable devices?(2) At what scale of the design hierarchy should fault tolerance be applied in high performance integrated systems?vi