Implementation of encryption algorithms on transport triggered architectures
P. Hamalainen, Marko Hännikäinen, Timo Hämäläinen, Henk Corporaal, J. Saarvinen · 2002
The paper studies a configurable processor architecture, transport triggered architecture (TTA), for encryption algorithm implementations. The automatic TTA design space exploration is applied and configurations with good cost-performance ratio are found. It is shown that TTAs are at least equal to commercial processors in performance. According to earlier studies the performance level is also achieved at far lower cost. This encourages further development with tuned functionality.