Use of BIST in Sun FireTM servers
J. Braden, Qing Lin, Brian Smith · International Test Conference · 2001
The latest UltraSPARCTM III generation of serversfrom Sun Microsystems makes extensive use ofBIST and other DFT techniques to help improvetest coverage and reduce test time during power-onself test. This lecture is a case study which willexamine a number of different BIST techniquesused in the Sun FireTM Midframe servers, and willshow how they were combined to improvediagnosis of faults and overall system availability.Specific DFT techniques which will be discussedinclude ASIC-based internal and external memoryBIST, ASIC logic BIST, microprocessor-controlledinterconnect test using IEEE 1149.1 boundaryscan, and at-speed interconnect BIST tests acrosssystem busses.The availability of a dedicated service processor inthe Sun FireTM Midframe Server systems providesa lot of flexibility in the reuse of ASIC tests at thesystem level. It also allows us to take advantage oftechniques like IEEE 1149.1 boundary scan basedinterconnect test without requiring an externaltester or complex partitioning of system logic. Wewill not attempt to describe any of the functionalarchitectural features of these servers, except asthey relate to the test problem we faced.The System Controller (SC) used in the SunFireTM[1] family is a microSPARCTM-II processorrunning a JavaOSTM operating system and itprovides the means by which all BIST testing iscontrolled and through which results are reported.This BIST and environmental testing is carried outunder control of JavaTM software running in theSC-APP, or System Controller Application layer.It contains classes and methods which implementIEEE 1149.1 functions like scan IR, scan DR andI2C select as well as communication functions toprovide remote access to these features. All powerup and initialization software is also run undercontrol of the System Controller, although it is notrequired for normal operation once a system is upand running applications. Each Sun FireTM servercan support either one or two (redundant) SystemControllers. The SC communicates with each ofthe system boards over a proprietary console bus.One or more ASICs on each of these boardscontains an IEEE 1149.1 master controller and anI2C controller to allow access to test andmonitoring functions on these boards. This testarchitecture is shown in Figure 1.