PRISM-a design for scalable shared memory
E. Kattamuri, Beng-Hong Lim, Pratap Pattnaik, Marc Snir · 1997
Summary form only given. This paper describes PRISM, a distributed shared-memory architecture that relies on a unified hardware and operating system structure for scalable and reliable performance. The PRISM system consists of multiple connected (UMA) shared memory multiprocessors, each controlled by its own kernel. Hardware and software are used to support coherent global shared memory segments, on top of this distributed architecture. PRISM's hardware provides flexible management and dynamic configuration of shared-memory pages with different behaviours. As an example, PRISM can manage shared-memory in both CC-NUMA and Simple-COMA styles. In the later case, the local memory at each node is used as a cache: allocation of cache memory is done by software, at a page granularity, while coherence is maintained by hardware, at a (L2) cache line granularity. In the former case, the L2 processor cache is directly backed up by remote memory. However, in both cases, the design does not require the usage of global memory management structures.